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 MC1496, MC1496B Balanced Modulators/ Demodulators
These devices were designed for use where the output voltage is a product of an input voltage (signal) and a switching function (carrier). Typical applications include suppressed carrier and amplitude modulation, synchronous detection, FM detection, phase detection, and chopper applications. See ON Semiconductor Application Note AN531 for additional design information.
Features
14 1
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SOIC-14 D SUFFIX CASE 751A
* Excellent Carrier Suppression -65 dB typ @ 0.5 MHz * * * * *
-50 dB typ @ 10 MHz Adjustable Gain and Signal Handling Balanced Inputs and Outputs High Common Mode Rejection -85 dB Typical This Device Contains 8 Active Transistors Pb-Free Package is Available*
14 1
PDIP-14 P SUFFIX CASE 646
PIN CONNECTIONS
Signal Input 1 Gain Adjust 2 Gain Adjust 3 Signal Input 4 Bias 5 Output 6 N/C 7 14 VEE 13 N/C 12 Output 11 N/C 10 Carrier Input 9 N/C 8 Input Carrier
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 12 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2004
1
April, 2004 - Rev. 9
Publication Order Number: MC1496/D
MC1496, MC1496B
0 IC = 500 kHz IS = 1.0 kHz Log Scale Id IC = 500 kHz, IS = 1.0 kHz 20
40 60 499 kHz 500 kHz 501 kHz
Figure 1. Suppressed Carrier Output Waveform
Figure 2. Suppressed Carrier Spectrum
10 8.0 Linear Scale 6.0 4.0 2.0 IC = 500 kHz IS = 1.0 kHz
IC = 500 kHz IS = 1.0 kHz
0 499 kHz 500 kHz 501 kHz
Figure 3. Amplitude Modulation Output Waveform
Figure 4. Amplitude-Modulation Spectrum
MAXIMUM RATINGS (TA = 25C, unless otherwise noted.)
Rating Applied Voltage (V6-V8, V10-V1, V12-V8, V12-V10, V8-V4, V8-V1, V10-V4, V6-V10, V2-V5, V3-V5) Differential Input Signal Maximum Bias Current Thermal Resistance, Junction-to-Air Plastic Dual In-Line Package Operating Ambient Temperature Range Storage Temperature Range Electrostatic Discharge Sensitivity (ESD) Human Body Model (HBM) Machine Model (MM) MC1496 MC1496B Symbol DV V8 - V10 V4 - V1 I5 RqJA TA Tstg ESD 2000 400 Value 30 +5.0 (5 + I5Re) 10 100 0 to +70 -40 to +125 -65 to +150 Unit Vdc Vdc mA C/W C C V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
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MC1496, MC1496B
ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, VEE = -8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 kW, Re = 1.0 kW, TA = Tlow to Thigh,
all input and output characteristics are single-ended, unless otherwise noted.) (Note 1) Characteristic Carrier Feedthrough VC = 60 mVrms sine wave and offset adjusted to zero VC = 300 mVpp square wave: offset adjusted to zero offset not adjusted Carrier Suppression fS = 10 kHz, 300 mVrms fC = 500 kHz, 60 mVrms sine wave fC = 10 MHz, 60 mVrms sine wave Transadmittance Bandwidth (Magnitude) (RL = 50 W) Carrier Input Port, VC = 60 mVrms sine wave fS = 1.0 kHz, 300 mVrms sine wave Signal Input Port, VS = 300 mVrms sine wave |VC| = 0.5 Vdc Signal Gain (VS = 100 mVrms, f = 1.0 kHz; | VC|= 0.5 Vdc) Single-Ended Input Impedance, Signal Port, f = 5.0 MHz Parallel Input Resistance Parallel Input Capacitance Single-Ended Output Impedance, f = 10 MHz Parallel Output Resistance Parallel Output Capacitance Input Bias Current I + I1 ) I4 ; I + I8 ) I10 bS bC 2 2 Input Offset Current IioS = I1-I4; IioC = I8-I10 Average Temperature Coefficient of Input Offset Current (TA = -55C to +125C) Output Offset Current (I6-I9) Average Temperature Coefficient of Output Offset Current (TA = -55C to +125C) Common-Mode Input Swing, Signal Port, fS = 1.0 kHz Common-Mode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc Common-Mode Quiescent Output Voltage (Pin 6 or Pin 9) Differential Output Voltage Swing Capability Power Supply Current I6 +I12 Power Supply Current I14 DC Power Dissipation 1. Tlow = 0C for MC1496 = -40C for MC1496B Thigh = +70C for MC1496 = +125C for MC1496B fC = 1.0 kHz fC = 10 MHz fC = 1.0 kHz fC = 1.0 kHz 5 2 VCS 40 - 8 8 BW3dB - - 10 6 3 - rip cip 6 - rop coo 7 - IbS IbC 7 7 7 7 9 9 10 10 7 7 - - - - 4 - - - 6 5 IioS IioC TCIio Ioo TCIoo CMV ACM Vout Vout ICC IEE PD - - - - - - - - - - - - - - 12 12 0.7 0.7 2.0 14 90 5.0 -85 8.0 8.0 2.0 3.0 33 30 30 7.0 7.0 - 80 - - - - - 4.0 5.0 - mA nA/C mA nA/C Vpp dB Vpp Vpp mAdc mW - - 40 5.0 - - kW pF m mA - - 200 2.0 - - kW pF AVS 2.5 300 80 3.5 - - - V/V 65 50 - - Fig. 5 Note 1 Symbol VCFT - - - - 40 140 0.04 20 - - mVrms 0.4 200 dB k MHz Min Typ Max Unit mVrms
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MC1496, MC1496B
GENERAL OPERATING INFORMATION
Carrier Feedthrough
Carrier feedthrough is defined as the output voltage at carrier frequency with only the carrier applied (signal voltage = 0). Carrier null is achieved by balancing the currents in the differential amplifier by means of a bias trim potentiometer (R1 of Figure 5).
Carrier Suppression
Note that in the test circuit of Figure 10, VS corresponds to a maximum value of 1.0 V peak.
Common Mode Swing
Carrier suppression is defined as the ratio of each sideband output to carrier output for the carrier and signal voltage levels specified. Carrier suppression is very dependent on carrier input level, as shown in Figure 22. A low value of the carrier does not fully switch the upper switching devices, and results in lower signal gain, hence lower carrier suppression. A higher than optimum carrier level results in unnecessary device and circuit carrier feedthrough, which again degenerates the suppression figure. The MC1496 has been characterized with a 60 mVrms sinewave carrier input signal. This level provides optimum carrier suppression at carrier frequencies in the vicinity of 500 kHz, and is generally recommended for balanced modulator applications. Carrier feedthrough is independent of signal level, VS. Thus carrier suppression can be maximized by operating with large signal levels. However, a linear operating mode must be maintained in the signal-input transistor pair - or harmonics of the modulating signal will be generated and appear in the device output as spurious sidebands of the suppressed carrier. This requirement places an upper limit on input-signal amplitude (see Figure 20). Note also that an optimum carrier level is recommended in Figure 22 for good carrier suppression and minimum spurious sideband generation. At higher frequencies circuit layout is very important in order to minimize carrier feedthrough. Shielding may be necessary in order to prevent capacitive coupling between the carrier input leads and the output leads.
Signal Gain and Maximum Input Level
The common-mode swing is the voltage which may be applied to both bases of the signal differential amplifier, without saturating the current sources or without saturating the differential amplifier itself by swinging it into the upper switching devices. This swing is variable depending on the particular circuit and biasing conditions chosen.
Power Dissipation
Power dissipation, PD, within the integrated circuit package should be calculated as the summation of the voltage-current products at each port, i.e. assuming V12 = V6, I5 = I6 = I12 and ignoring base current, PD = 2 I5 (V6 - V14) + I5)V5 - V14 where subscripts refer to pin numbers.
Design Equations
The following is a partial list of design equations needed to operate the circuit with other supply voltages and input conditions. A. Operating Current The internal bias currents are set by the conditions at Pin 5. Assume: I5 = I6 = I12, IBtt IC for all transistors then :
where: R5 is the resistor between V * *f *500 W where: Pin 5 and ground I5 where: f = 0.75 at TA = +25C
R5+
The MC1496 has been characterized for the condition I5 = 1.0 mA and is the generally recommended value. B. Common-Mode Quiescent Output Voltage
V6 = V12 = V+ - I5 RL Biasing
Signal gain (single-ended) at low frequencies is defined as the voltage gain,
A VS + R Vo L + where r e + 26 mV R e)2r e V I5(mA) S
A constant dc potential is applied to the carrier input terminals to fully switch two of the upper transistors "on" and two transistors "off" (VC = 0.5 Vdc). This in effect forms a cascode differential amplifier. Linear operation requires that the signal input be below a critical value determined by RE and the bias current I5.
VS p I5 RE (Volts peak)
The MC1496 requires three dc bias voltage levels which must be set externally. Guidelines for setting up these three levels include maintaining at least 2.0 V collector-base bias on all transistors while not exceeding the voltages given in the absolute maximum rating table; 30 Vdc w [(V6, V12) - (V8, V10)] w 2 Vdc 30 Vdc w [(V8, V10) - (V1, V4)] w 2.7 Vdc 30 Vdc w [(V1, V4) - (V5)] w 2.7 Vdc The foregoing conditions are based on the following approximations:
V6 = V12, V8 = V10, V1 = V4
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MC1496, MC1496B
Bias currents flowing into Pins 1, 4, 8 and 10 are transistor base currents and can normally be neglected if external bias dividers are designed to carry 1.0 mA or more.
Transadmittance Bandwidth Negative Supply
VEE should be dc only. The insertion of an RF choke in series with VEE can enhance the stability of the internal current sources.
Signal Port Stability
Carrier transadmittance bandwidth is the 3.0 dB bandwidth of the device forward transadmittance as defined by:
g21C+ i o (each sideband) v s (signal)
Vo + 0
Signal transadmittance bandwidth is the 3.0 dB bandwidth of the device forward transadmittance as defined by:
i o (signal) g21S+ v (signal) s
Under certain values of driving source impedance, oscillation may occur. In this event, an RC suppression network should be connected directly to each input using short leads. This will reduce the Q of the source-tuned circuits that cause the oscillation.
Signal Input (Pins 1 and 4)
Vc + 0.5 Vdc, Vo + 0
510 10 pF
Coupling and Bypass Capacitors
Capacitors C1 and C2 (Figure 5) should be selected for a reactance of less than 5.0 W at the carrier frequency.
Output Signal
The output signal is taken from Pins 6 and 12 either balanced or single-ended. Figure 11 shows the output levels of each of the two output sidebands resulting from variations in both the carrier and modulating signal inputs with a single-ended output connection.
An alternate method for low-frequency applications is to insert a 1.0 kW resistor in series with the input (Pins 1, 4). In this case input current drift may cause serious degradation of carrier suppression.
TEST CIRCUITS
1.0 k C1 0.1 mF 1.0 k Re 51 C2 Carrier Input 0.1 mF VC VS Modulating Signal Input 10 k R1 Carrier Null 8 10 1 4 51 2 1.0 k 3 RL 3.9 k I9 I6 MC1496 14 I10 V- -8.0 Vdc VEE I5 5 6.8 k
NOTE:
VCC 12 Vdc RL 3.9 k +V o -V o Zin 0.5 V 8 + - 10 1 4 2
Re = 1.0 k 3 MC1496 14 5 6.8 k -8.0 Vdc
Shielding of input and output leads may be needed to properly perform these tests.
6 12
+V o Zout -V o
6 12
10 k 51 50 k
Figure 5. Carrier Rejection and Suppression
VCC 12 Vdc Re = 1.0 k 1.0 k I7 I8 I1 I4 8 10 1 4 2 MC1496 14 I10 5 6.8 k 3 I6 6 12 I9 2.0 k Carrier Input 0.1 mF VC VS Modulating Signal Input 10 k
Figure 6. Input-Output Impedance
1.0 k 51 0.1 mF 8 10 1 4 10 k 50 k Carrier Null V- -8.0 Vdc VEE 51 51 1.0 k Re 2 1.0 k 3 6 12 14 5 6.8 k VCC 12 Vdc 2.0 k 50 50 0.01 mF +V o -V o
1.0 k
MC1496
-8.0 Vdc VEE
Figure 7. Bias and Offset Currents
Figure 8. Transconductance Bandwidth http://onsemi.com
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MC1496, MC1496B
VCC 12 Vdc 1.0 k Re = 1.0 k 3.9 k 3.9 k 1.0 k +V o -V o VS 50 50 -8.0 Vdc VEE 6.8 k V A + 20 log o CM V S 8 + - 10 1 4 0.5 V 1.0 k 2 MC1496 14 I5 = 1.0 mA -8.0 Vdc VEE 5 6.8 k Re = 1.0 k 3 3.9 k 3.9 k +V o -V o VCC 12 Vdc
1.0 k VS
3 0.5 V 8 2 + - 10 1 MC1496 6 4 12 14 5
6 12
Figure 9. Common Mode Gain
Figure 10. Signal Gain and Output Swing
TYPICAL CHARACTERISTICS
VO , OUTPUT AMPLITUDE OF EACH SIDEBAND (Vrms) Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave), VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25C, unless otherwise noted. 2.0 1.6 1.2 0.8 0.4 0 0 50 100 150 VC, CARRIER LEVEL (mVrms) 200 Signal Input = 600 mV 400 mV 300 mV 200 mV 100 mV 1.0 M r ip, PARALLEL INPUT RESISTANCE (k ) 500 +rip 100 50 -rip
10 5.0
1.0 1.0
5.0 10 f, FREQUENCY (MHz)
50
100
Figure 11. Sideband Output versus Carrier Levels
cip , PARALLEL INPUT CAPACITANCE (pF)
Figure 12. Signal-Port Parallel-Equivalent Input Resistance versus Frequency
cop, PARALLEL OUTPUT CAPACITANCE (pF)
rop , PARALLEL OUTPUT RESISTANCE (k )
5.0 4.0 3.0 2.0 1.0 0 1.0
140 120 100 80 60 40 20 0 0 1.0 10 f, FREQUENCY (MHz) cop rop
14 12 10 8.0 6.0 4.0 2.0 0 100
2.0
20 10 5.0 f, FREQUENCY (MHz)
50
100
Figure 13. Signal-Port Parallel-Equivalent Input Capacitance versus Frequency
Figure 14. Single-Ended Output Impedance versus Frequency
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MC1496, MC1496B
TYPICAL CHARACTERISTICS (continued)
Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave), VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25C, unless otherwise noted.
21, TRANSADMITTANCE (mmho)
VCS, CARRIER SUPPRESION (dB)
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1
0 Signal Port 10 20 30 40 50 60 70 -75 -50 -25 0 25 50 75 100 125 150 175 MC1496 (70C)
Side Band Sideband Transadmittance I out (Each Sideband) g21 + V out + 0 V (Signal) in
Signal Port Transadmittance I g21 + out V out + 0 |V | + 0.5 Vdc C V in 10 1.0 100 fC, CARRIER FREQUENCY (MHz)
1000
TA, AMBIENT TEMPERATURE (C)
Figure 15. Sideband and Signal Port Transadmittances versus Frequency
Figure 16. Carrier Suppression versus Temperature
AVS , SINGLE-ENDED VOLTAGE GAIN (dB)
20 10 0 -10 |VC| = 0.5 Vdc -20 -30 0.01 RL = 3.9 k (Standard Re = 1.0 k Test Circuit)
RL = 3.9 k Re = 500 W
SUPPRESSION BELOW EACH FUNDAMENTAL CARRIER SIDEBAND (dB)
0 10 20 30 40 50 fC 60 70 0.05 0.1 3fC 0.5 1.0 5.0 10 fC, CARRIER FREQUENCY (MHz) 50 2fC
RL = 3.9 k Re = 2.0 k RL = 500 W Re = 1.0 k R
L A+ V R e ) 2r e 0.1 1.0 f, FREQUENCY (MHz) 10 100
Figure 17. Signal-Port Frequency Response
Figure 18. Carrier Suppression versus Frequency
VCFT , CARRIER OUTPUT VOLTAGE (mVrms)
SUPPRESSION BELOW EACH FUNDAMENTAL CARRIER SIDEBAND (dB)
10
0 10 20 30 40 50 60 70 80 0 200 400 600 VS, INPUT SIGNAL AMPLITUDE (mVrms) 800 fC 3fS fC 2fS
1.0
0.1
0.01 0.05
0.1
0.5 1.0 5.0 10 fC, CARRIER FREQUENCY (MHz)
50
Figure 19. Carrier Feedthrough versus Frequency
Figure 20. Sideband Harmonic Suppression versus Input Signal Level
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MC1496, MC1496B
SUPPRESSION BELOW EACH FUNDAMENTAL CARRIER SIDEBAND (dB) 0 10 20 30 40 50 60 70 0.05 0.1 0.5 1.0 5.0 10 fC, CARRIER FREQUENCY (MHz) 50 2fC fS 2fC 2fS 3fC fS V CS , CARRIER SUPPRESSION (dB) 0 10 20 30 40 50 60 70 0 100 200 300 400 VC, CARRIER INPUT LEVEL (mVrms) 500 fC = 500 kHz fC = 10 MHz
Figure 21. Suppression of Carrier Harmonic Sidebands versus Carrier Frequency
Figure 22. Carrier Suppression versus Carrier Input Level
OPERATIONS INFORMATION The MC1496, a monolithic balanced modulator circuit, is shown in Figure 23. This circuit consists of an upper quad differential amplifier driven by a standard differential amplifier with dual current sources. The output collectors are cross-coupled so that full-wave balanced multiplication of the two input voltages occurs. That is, the output signal is a constant times the product of the two input signals. Mathematical analysis of linear ac signal multiplication indicates that the output spectrum will consist of only the sum and difference of the two input frequencies. Thus, the device may be used as a balanced modulator, doubly balanced mixer, product detector, frequency doubler, and other applications requiring these particular output signal characteristics. The lower differential amplifier has its emitters connected to the package pins so that an external emitter resistance may be used. Also, external load resistors are employed at the device output.
Signal Levels
The upper quad differential amplifier may be operated either in a linear or a saturated mode. The lower differential amplifier is operated in a linear mode for most applications. For low-level operation at both input ports, the output signal will contain sum and difference frequency
(-) 12 (+) 6 Carrier V Input C 10 (-) 8 (+) 2 3 Bias 5 500 VEE 14 500 500 (Pin numbers per G package) Gain Adjust Vo, Output
components and have an amplitude which is a function of the product of the input signal amplitudes. For high-level operation at the carrier input port and linear operation at the modulating signal port, the output signal will contain sum and difference frequency components of the modulating signal frequency and the fundamental and odd harmonics of the carrier frequency. The output amplitude will be a constant times the modulating signal amplitude. Any amplitude variations in the carrier signal will not appear in the output. The linear signal handling capabilities of a differential amplifier are well defined. With no emitter degeneration, the maximum input voltage for linear operation is approximately 25 mV peak. Since the upper differential amplifier has its emitters internally connected, this voltage applies to the carrier input port for all conditions. Since the lower differential amplifier has provisions for an external emitter resistance, its linear signal handling range may be adjusted by the user. The maximum input voltage for linear operation may be approximated from the following expression:
V = (I5) (RE) volts peak.
This expression may be used to compute the minimum value of RE for a given input voltage amplitude.
1.0 k 51 V 0.1 mF Carrier C Input VS Modulating Signal 10 k Input 8 10 1 4 10 k 50 k I5 Carrier Null -8.0 Vdc VEE 6.8 k 51 51 1.0 k 0.1 mF 2 Re 1.0 k 3 RL 3.9 k 6 MC1496 12 14 5 -Vo 12 Vdc RL 3.9 k +Vo
4 (-) Signal V S 1 (+) Input
Figure 23. Circuit Schematic
Figure 24. Typical Modulator Circuit
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MC1496, MC1496B
Table 1. Voltage Gain and Output Frequencies
Carrier Input Signal (VC) Approximate Voltage Gain RV LC 2(R ) 2r e) KT q E R L R ) 2r e E R V (rms) LC KT (R ) 2r ) 22 q e E Output Signal Frequency(s)
Low-level dc
fM
High-level dc
fM
Low-level ac
fC fM
2. 3. 4. 5. 6. 7.
0.637 R L fC fM, 3fC fM, 5fC fM, . . . R ) 2r e E Low-level Modulating Signal, VM, assumed in all cases. VC is Carrier Input Voltage. When the output signal contains multiple frequencies, the gain expression given is for the output amplitude ofeach of the two desired outputs, fC + fM and fC - fM. All gain expressions are for a single-ended output. For a differential output connection, multiply each expression by two. RL = Load resistance. RE = Emitter resistance between Pins 2 and 3. re = Transistor dynamic emitter resistance, at 25C; 26 mV High-level ac
re [ I5 (mA)
8. K = Boltzmanns Constant, T = temperature in degrees Kelvin, q = the charge on an electron.
The gain from the modulating signal input port to the output is the MC1496 gain parameter which is most often of interest to the designer. This gain has significance only when the lower differential amplifier is operated in a linear mode, but this includes most applications of the device. As previously mentioned, the upper quad differential amplifier may be operated either in a linear or a saturated mode. Approximate gain expressions have been developed for the MC1496 for a low-level modulating signal input and the following carrier input conditions: 1) Low-level dc 2) High-level dc 3) Low-level ac 4) High-level ac These gains are summarized in Table 1, along with the frequency components contained in the output signal. APPLICATIONS INFORMATION Double sideband suppressed carrier modulation is the basic application of the MC1496. The suggested circuit for this application is shown on the front page of this data sheet. In some applications, it may be necessary to operate the MC1496 with a single dc supply voltage instead of dual supplies. Figure 25 shows a balanced modulator designed for operation with a single 12 Vdc supply. Performance of this circuit is similar to that of the dual supply modulator.
AM Modulator
All that is required to shift from suppressed carrier to AM operation is to adjust the carrier null potentiometer for the proper amount of carrier insertion in the output signal. However, the suppressed carrier null circuitry as shown in Figure 26 does not have sufficient adjustment range. Therefore, the modulator may be modified for AM operation by changing two resistor values in the null circuit as shown in Figure 27.
Product Detector
The circuit shown in Figure 26 may be used as an amplitude modulator with a minor modification.
The MC1496 makes an excellent SSB product detector (see Figure 28). This product detector has a sensitivity of 3.0 mV and a dynamic range of 90 dB when operating at an intermediate frequency of 9.0 MHz. The detector is broadband for the entire high frequency range. For operation at very low intermediate frequencies down to 50 kHz the 0.1 mF capacitors on Pins 8 and 10 should be increased to 1.0 mF. Also, the output filter at Pin 12 can be tailored to a specific intermediate frequency and audio amplifier input impedance. As in all applications of the MC1496, the emitter resistance between Pins 2 and 3 may be increased or decreased to adjust circuit gain, sensitivity, and dynamic range. This circuit may also be used as an AM detector by introducing carrier signal at the carrier input and an AM signal at the SSB input. The carrier signal may be derived from the intermediate frequency signal or generated locally. The carrier signal may
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MC1496, MC1496B
be introduced with or without modulation, provided its level is sufficiently high to saturate the upper quad differential amplifier. If the carrier signal is modulated, a 300 mVrms input level is recommended.
Doubly Balanced Mixer
Figures 30 and 31 show a broadband frequency doubler and a tuned output very high frequency (VHF) doubler, respectively.
Phase Detection and FM Detection
The MC1496 may be used as a doubly balanced mixer with either broadband or tuned narrow band input and output networks. The local oscillator signal is introduced at the carrier input port with a recommended amplitude of 100 mVrms. Figure 29 shows a mixer with a broadband input and a tuned output.
Frequency Doubler
The MC1496 will operate as a frequency doubler by introducing the same frequency at both input ports.
The MC1496 will function as a phase detector. High-level input signals are introduced at both inputs. When both inputs are at the same frequency the MC1496 will deliver an output which is a function of the phase difference between the two input signals. An FM detector may be constructed by using the phase detector principle. A tuned circuit is added at one of the inputs to cause the two input signals to vary in phase as a function of frequency. The MC1496 will then provide an output which is a function of the input signal frequency.
TYPICAL APPLICATIONS
1.0 k
820 0.1 mF 0.1 mF 51 8 10 1 4
1.3 k 3.0 k 3 6 MC1496 12 10 k
VCC 12 Vdc 3.0 k DSB 0.1 mF Output 51 VC 0.1 mF Carrier Input VS Modulating 10 k Signal Input 1.0 k 1.0 k 0.1 mF 2 8 10 1 4 51 51 14 I5 VEE -8.0 Vdc Re 1.0 k RL 3 3.9 k 6 MC1496 12 10 k 50 k R1 Carrier Null 5 6.8 k - VCC 12 Vd RL 3.9 +
25 mF 15 V Carrier Input 60 mVrms Modulating -
+
2 1.0 k
+
Signal Input 10 mF 300 mVrms 15 V Carrier Null 50 k 10 k 10 k 100
25 mF 14 15 V +- 100
5
Figure 25. Balanced Modulator (12 Vdc Single Supply)
Figure 26. Balanced Modulator-Demodulator
1.0 k 51 VC 0.1 mF Carrier Input VS Modulating Signal 750 Input
1.0 k RL 0.1 mF 2 Re 1.0 k 3 3.9 k 8 6 10 1 MC1496 4 12 51 51 14 5 15 6.8 k VEE -8.0 Vdc
VCC 12 Vdc RL 3.9 k 1.0 k
820 0.1 mF 8 0.1 mF 10 1 1.0 k 4 0.1 mF 1.0 k 0.1 mF 51 2
1.3 k 100
VCC 12 Vdc 3.0 k 6 3.0 k 0.005 mF AF 1.0 k 1.0 mF Outp RLq 10 0.005 0.005 mF mF
3
+Vo Carrier Input 300 mVrms -Vo SSB Input
MC1496 14 5 12 10 k
750 50 k
Carrier Adjust
Figure 27. AM Modulator Circuit
Figure 28. Product Detector (12 Vdc Single Supply)
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MC1496, MC1496B
VCC 12 Vdc + 1.0 k - 1.0 k C2 100 mF 25 Vdc 8 100 10 MC1496 12 14 5 6.8 k I5
L1 = 44 Turns AWG No. 28 Enameled Wire, Wound on Micrometals Type 44-6 Toroid Core.
1.0 k 0.001 mF Local Oscillator Input 100 mVrms RF Input 10 k 51 10 k 51 50 k Null Adjust 2 8 10 0.001 mF 1 51 4
1.0 k 0.01 mF 6 MC1496 12 5 5.0-80 pF 6.8 k VEE -8.0 Vdc
VCC +8.0 Vdc RFC 100 mH 0.001 mF 9.5 mF L1
3
2
1.0 k
3
3.9 k 3.9 k 6 Outp
14
9.0 MHz Output RL = 50W
100 mF - C2+ Input 15 Vdc Max 100 mF 15 Vdc 15 mVrms 1 4 10 k 50 k 10 k 100 100
90-480 pF
Balance
VEE -8.0 Vdc
Figure 29. Doubly Balanced Mixer (Broadband Inputs, 9.0 MHz Tuned Output)
Figure 30. Low-Frequency Doubler
1.0 k
1.0 k 0.001 mF 2 3
V+ 18 pF RFC 0.68 mH 6
VCC +8.0 Vdc
100 0.001 mF 150 MHz Input 100 10 k 10 k 50 k Balance
0.001 mF 8 10 1 4
L1 18 nH 1.0-10 pF 1.0-10 pF
MC1496 12
300 MHz Output RL = 50W
100 14
5 6.8 k
L1 = 1 Turn AWG No. 18 Wire, 7/32 ID
VEE -8.0 Vdc
Figure 31. 150 to 300 MHz Doubler
(fC - f S )
AMPLITUDE
(fC + f S )
(2fC + 2f S )
(2fC - 2f S )
(3fC - 2f S ) (3fC - fS )
(2fC - 2f S )
(2fC + 2f S )
(3fC + f S ) (3f C )
Frequency
fC fS fC fS Carrier Fundamental Modulating Signal Fundamental Carrier Sidebands
Balanced Modulator Spectrum DEFINITIONS
fC nfS Fundamental Carrier Sideband Harmonics Carrier Harmonics nfC nfC nfS Carrier Harmonic Sidebands
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(2fC )
(3fC + 2f S )
(fC - 2f S )
(f + 2f ) C S
(fC )
MC1496, MC1496B
ORDERING INFORMATION
Device MC1496D MC1496DR2 MC1496DR2G MC1496P MC1496PG MC1496P1 MC1496BD MC1496BDR2 MC1496BP Package SOIC-14 SOIC-14 SOIC-14 (Pb-Free) PDIP-14 PDIP-14 (Pb-Free) PDIP-14 SOIC-14 SOIC-14 PDIP-14 Shipping 55 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 25 Units/Rail 25 Units/Rail 25 Units/Rail 55 Units/Rail 2500 Tape & Reel 25 Units/Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
SOIC-14 D SUFFIX CASE 751A 14 MC1496D AWLYWW 1 1 14 MC1496BD AWLYWW 1 14 MC1496P AWLYYWW
PDIP-14 P SUFFIX CASE 646 14 MC1496BP AWLYYWW 1
A WL YY, Y WW
= Assembly Location = Wafer Lot = Year = Work Week
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MC1496, MC1496B
PACKAGE DIMENSIONS
-A-
14 8
SOIC-14 D SUFFIX PLASTIC PACKAGE CASE 751A-03 ISSUE F
-B- P 7 PL 0.25 (0.010)
M
1
7
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
14
8
PDIP-8 P SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE M
B
1
7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01
A F N -T-
SEATING PLANE
L C
K H G D 14 PL 0.13 (0.005)
M
J M
DIM A B C D F G H J K L M N
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MC1496, MC1496B
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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MC1496/D


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